Industrial PLC programmers face many problems. Among them: reducing scan time so lower cost PLCs can be used; eliminating 'bugs' in ladder logic rungs; and reducing maintenance costs on old ladder logic.

Karnaugh mapping can help with all these problems. Karnaugh mapping is a systematic and pictorial way of applying Boolean algebra to reduce complex digital problems.

An example of Karnaugh mapping could begin with writing an organized statement about the conditions for going on a picnic. In this case, the alternatives are Sunday and Clear and Calm or Sunday and Clear and Windy. Common sense analysis of the logic says it doesn't matter whether the wind blows, so the picnic statement becomes Sunday and Clear, a much simpler statement (see diagram).

The picnic statement in ladder logic looks something like this:

As the ladder logic shows, the picnic rung is enabled whether it is calm or not calm-so the rung can be written in a simpler form that reduces scan time:

More complicated programs require a more systematic approach for analysis. The principles of Boolean algebra fit that requirement.

The first step is to make a clear problem statement. The next step is to construct a truth table. The truth table uses all combinations of all variables of the problem-day of week, cloudiness, and wind conditions.

An example of the truth table for the picnic problem includes numeric representations in a binary form that make the truth table easier to manipulate.

A truth table has a column for every variable. When you let the number of variables = n, a truth table has 2 to the power n rows.

The next step is to construct a Karnaugh (K) map. The K map is square or rectangular in the proportions 2 to 1 and contains 2 to the n squares-one for each row of the truth table. The three-variable map for our picnic problem is rectangular and has eight squares-one for each row of the truth table.

The squares are numbered the same as the rows on the truth table. However, there is a method to the numbering-such that rows represented by the numbers vary by only one variable in adjacent squares. In this way, adjacent squares represent variables that can be removed.

The following is a typical three-variable map:

Now, the picnic's truth table can be mapped on the three-variable K map. Row numbers on the truth table correspond exactly to square numbers in the K map. Each square also has a three-digit binary number for the row on the truth table. Notice that adjacent squares vary by only one bit. The result number is represented in bold type.

The two paths of ladder logic are represented by lines six and seven on the truth table. Their appearance in adjacent squares on the K map indicates a condition for rung (logic) reduction. The entire rung is represented by A and B (the first and second bits) with bit C being superfluous. Therefore, if A and B are true, then we go on the picnic! This is the same result we got by applying common sense.

K maps work, but isn't common sense faster? For this level of problem, yes. However, we are laying a foundation for more challenging problems using and establishing a design methodology.

Back in the early days of computers and integrated circuits-after discrete components and before microprocessors-computer integrated circuits were built with bit slice Arithmetic Logic Units. Suppose we have a simple PLC with no math instructions and we need to add two eight-bit numbers. Do we spend $5,000 for a capable PLC or is there some technology that we can use to save money?

The specification calls for a bit slice adder. A truth table for one slice woud look like this:

For this problem, two three-variable maps are needed, one for the Carry out and one for the Sum.

The ladder logic from the equation would look like this:

Putting it together-an 8-bit adder

Maintenance follows much the same approach as design, except that a truth table must be constructed from the old rung. A traditionally designed rung such as:

would have a truth table that looks like this:

The truth table can then be maintenanced and K mapped to form the new rung.

The next step in PLC logic minimization may be to devise rung software or a hand held rung calculator to perform rung minimization. If PLC manufacturers decide to include this rung minimization software in their design packages, a handheld rung calculator would soon become obsolete. A feature of a rung minimization algorithm is rung entry and optimization using the engineer's favorite methods.

Good luck and good logic!

For more information, a good book on Karnaugh mapping is Computer Logic Design by M. Morris Mano, Prentice Hall, 1972. For a more complete Karnaugh mapping discussion, visit www.controleng.com .