New HDL code generation capabilities simplify programming for ASICs and FPGAs
MathWorks adds HDL code generating and verification capabilities to Matlab and Simulink to simplify development work for system designers.
MathWorks has announced HDL Coder, which automatically generates HDL code from Matlab, allowing engineers to implement FPGA (field-programmable gate array) and ASIC (application-specific integrated circuit) designs from that language. MathWorks also announced HDL Verifier, which includes FPGA hardware-in-the-loop capabilities for testing FPGA and ASIC designs. With these two products, MathWorks now provides HDL code generation and verification across Matlab and Simulink.
“Engineers everywhere use Matlab and Simulink to design systems and algorithms,” said Tom Erkkinen, embedded applications and certification manager, MathWorks. “Now, with HDL Coder and HDL Verifier, they no longer have to manually write HDL code or test benches to develop FPGA and ASIC designs.”
HDL Coder generates portable, synthesizable VHDL and Verilog code from Matlab functions and Simulink models that can be used for FPGA programming or ASIC prototyping and design. As a result, engineering teams can now identify the best algorithm for hardware implementation. Traceability between Simulink models and generated HDL code also supports the development of high-integrity applications that adhere to DO-254 and other standards.
“HDL Coder offers integration with Xilinx ISE design suite, creating a pushbutton workflow that makes it easy for algorithm developers who use MathWorks products to target Xilinx FPGAs,” said Vin Ratford, Sr. vice president of worldwide marketing and business development for Xilinx. “This integration also provides our mutual customers access to a broad portfolio of Xilinx optimized IP from within HDL Coder that further accelerates their productivity.”
HDL Verifier now supports FPGA hardware-in-the-loop verification for Altera and Xilinx FPGA boards. HDL Verifier provides co-simulation interfaces that link Matlab and Simulink with Cadence Incisive, Mentor Graphics ModelSim, and Questa HDL simulators. With these capabilities, engineers can rapidly verify that their HDL implementation matches their Matlab algorithms and Simulink system specifications.
“As adoption of FPGAs continues to grow across industries, designers need a way to bridge the verification gap from system models to FPGA design,” said Vince Hu, vice president of product and corporate marketing at Altera. “HDL Verifier links system models to FPGA designs and enables engineers to perform FPGA hardware-in-the-loop verification with Altera FPGAs and Simulink. This workflow shortens verification cycles and helps engineers gain greater confidence in their silicon implementations.”
Edited by Peter Welander, pwelander(at)cfemedia.com
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