Power Management Balances Performance and Consumption

An ever-increasing number of transistors and more performance being squeezed into chip-level products (and embedded microprocessors) of shrinking physical size are unmasking a critical power consumption issue. Power usage rather than operating speed is becoming the performance bottleneck, as silicon device production continues to shrink to 90 nanometer (nm), 65 nm, and even smaller process nodes.

06/01/2006


AT A GLANCE

 

  • Chip power management

  • Embedded control

  • Leakage power

  • Multi-core processors

  • Strained silicon

An ever-increasing number of transistors and more performance being squeezed into chip-level products (and embedded microprocessors) of shrinking physical size are unmasking a critical power consumption issue. Power usage rather than operating speed is becoming the performance bottleneck, as silicon device production continues to shrink to 90 nanometer (nm), 65 nm, and even smaller process nodes.

A basic tenet of chip power management is that not all functions or resources of these devices need to be powered simultaneously or all of the time. A variety of techniques is being applied to implement this principle. In addition, innovative new methods are in the works to attack power consumption at the silicon substrate, process, and system levels.

The problem is daunting; prospects for solutions are high.

Multi-core movement

Ability to modify functions to suit operating conditions is one way to keep power usage in check. Intel Corp.'s most recent approach in this area takes the form of multi-core technology—integrating multiple, independent processing cores on one silicon die or package. The architecture permits flexible power distribution over the chip; for example, one core could be doing multithreading, while parts of another core are turned off in a given application to reduce power. Having two (or more) cores available adds to overall flexibility to adjust power usage.

"A 'core-hopping mechanism' is available to distribute tasks across multiple cores, hence spread power dissipation over a greater die area," explains Phil Ames, marketing manager for Intel's Infrastructure Processing Div. "Multi-core processors [also] can be clocked at slower speeds and supplied with lower voltage to yield greater performance per watt." While single-core chips can operate at lower speed and voltage as well, ability to turn functions off and on is not as efficient, he adds.

Intel further notes that lower operating speed/voltage and more distributed tasks reduce the "cost of thermal solutions required to maintain reliability" of these devices because they're not as thermally stressed as single-core devices.

Embedded Control

Said to be unique to AMD’s Opteron processors, five power states help cut average CPU core power to match performance to the application. Voltage stepdown is the prime factor for power reduction.

Advanced Micro Devices Inc. (AMD) also is moving to dual-core technology. Placing another core on the same chip doesn't appreciably change power and thermal envelopes because AMD64 architecture "was designed from the ground up with multiple cores in mind," explains Brent Kerby, product manager, AMD Opteron. Power consumption can be mitigated by appropriate integration of the extra core(s) into the architecture. How is it done? Reduce core-level voltage and frequency, somewhat, to gain performance due to the additional core. "Tradeoffs among speed, voltage, and power usage are constantly going on," he says. Importantly, maximum power is held to 95 W (for single- and dual-core), which includes powering the memory controller. It's substantially lower than competing chip products, according to Kerby.

"With multi-threaded workloads in the server segment, adding more cores with minimal changes in power and thermal requirements provides increased computational performance, potentially reducing the number of energy consuming processors required within a given platform," says Kerby.

AMD believes that processor power management techniques have drawn intense focus over the past few years. In the server segment, some items remain to be optimized for energy efficiency at the chip-level, he states. Some platform-level infrastructure could also benefit from efficiency improvement. Kerby lists memory technologies, voltage regulator modules for processors and memory, and especially power supplies—many of which offer only 70% efficiency—in this category.

A growing issue

Freescale Semiconductor Inc. sees power management as a growing, albeit manageable issue for design engineers. It's manageable—suggests Jeff Bock, Freescale global marketing manager, 16/32-bit consumer and industrial operations—if silicon and hardware development allows designers to "selectively choose" among which functions, speeds, and operating times.

Two basic solution paths exist and require simultaneous implementation, according to Bock. First, hardware options are available for flexible power management. For example, chips such as Freescale's ColdFire microcontroller family offer an array of power management methods, among them:

  • Flexible clock gating (ability to turn off clocks at the chip level and within sections of the core, depending on application);

  • Power management modules to turn off sections of the chip not being used; and

  • Bypass clocking to run some parts down at nearly dc levels (well under 1 kHz) for ultra-low power operation, not possible with standard clocking.

"Selecting processors with power-management options, opens the door to managing the power conundrum," Bock says.

Second, designers need to know how to enable various processor options for optimal power usage. This requires tools (compilers, debuggers), training, and collateral material, such as application notes or other Web/paper-based tools as an aid to designers. "Software design techniques can enter into the equation as well; writing code to run efficiently, quickly, and to minimize system resource usage can also dramatically impact system power usage," states Bock.

Addressing idle mode

Atmel Corp., a leading developer of advanced semiconductors and microcontrollers (MCUs), is also active in power management techniques. Its recent AVR picoPower technology addresses numerous applications that reside in idle mode much of the time, such as battery-powered devices; yet, they have features drawing non-useful power even in sleep mode.

MCUs with picoPower claim superior low-power consumption relative to competing controllers. Typical current usage is down to 340

Among notable features of picoPower technology is a brown-out detector (BOD), unusual because it has its own sleep mode. BODs sense the power supply's operating voltage threshold and provide a reset signal in case of power failure, preventing loss of valuable data and controller damage. BODs fall into types, explains Bård M. Pedersen, AVR product manager—"Zero- or low-power units with very low performance/accuracy; and faster, more accurate but power-consuming units." Also, most BODs stay active in processor sleep mode. This causes significant power drain, especially for battery-powered devices, leading most low-power MCU producers to opt for lower current consumption over speed and accuracy in their BOD, according to Atmel.

A different approach at Atmel allows automatic disabling of the BOD during sleep mode, when this function is not needed. However, the circuit's fast response (2h provides superior protection with substantially less power drain," Pedersen adds.

Among its solutions, Intel cites active power management methods that cut power requirements by "putting to sleep" modules on devices or in the system during times they're not needed in an application. As an example, "Enhanced Intel SpeedStep Technology" allows dynamic adjustment of processor voltage and core frequency, resulting in less power consumption, which leads to decreased heat generation—hence improved acoustics as system-level fans need not spin as fast. Also, a new power-savings mechanism in Intel Core Duo processors (photo) enables the dual-core device's shared cache to dynamically flush its information lines into system memory—depending on demand or during inactive periods. "Power savings occur as cache ways are turned off once the data have been saved in memory," states Intel's Ames. "This is accomplished without adversely impacting users perception of adequate performance.

Longer-term directions

"A microprocessor accounts for only a portion of total system power demands, which engineering teams must evaluate in all its aspects and [as it relates to] expected performance levels. Once requirements are understood, specific functions can be redistributed/offloaded to balance performance with power efficiency and/or footprint requirements," he adds.

Aside from multi-core technology, Intel is active in other power efficiency methods—such as reducing leakage current. Ames mentions work with high-k dielectric materials and different gate metals to combat leakage current, an issue becoming critical at smaller silicon process nodes. Using high-k dielectrics, Intel claims 100 times less leakage current compared to a traditional silicon dioxide dielectric.

Another newer way to boost power efficiency (and chip performance) is a process that forces silicon atoms apart in the semiconductor material to allow less restricted flow of electrons. Known as "strained silicon," it yields less power consumption and less heat generation. Ames notes a five-fold reduction of leakage current using Intel's proprietary strained silicon, and a further four-times reduction with its second-generation strained silicon as the company scales to the 65-nm process.

PC-based Control

Effect of operating frequency on power consumption is shown for Freescale Semiconductor’s MCF5213 devices under two low-power modes—run and wait/doze. SRAM version consumes substantially less power than flash memory at all frequencies. Measurements were made at room
temperature.

At AMD, ongoing power management methods range from the granular performance-state (reduced core voltage and frequency) to fine-grain approaches. This includes the block level, where certain chip sections can be shut down optimally during unused periods, and clock gating at individual transistors—for example—that take "power management to the farthest extent possible," according to Kerby. "These techniques will be applied to devices outside the CPU to a greater extent than today."

One such external device, the memory controller, has been integrated into the processor by AMD to obtain benefits of direct connection of memory to CPU, I/O to CPU, and CPUs to CPUs, for more linear symmetrical multiprocessing—as well as lower power consumption. Kerby emphasizes that maximum power state of dual-core AMD Opteron processors, at 95 W, includes the memory controller.

Other factors related to power management, such as footprint, leakage current, or role of development tools, are weighted and considered in defining capabilities of each generation of products. "We take a systematic approach and focus our efforts on areas that will provide the greatest improvement," adds Kerby.

As a silicon manufacturer, Freescale views power control from a perspective of innovation on three fronts: process technology, more flexible new chip designs, and training/tools for optimizing system power around its architectures. Process technology involves continuing to reduce leakage currents and run currents for devices at all performance levels—a task "inherently simpler" for lower-performance devices, explains Bock.

"Newer, cutting-edge process technologies (90 nm) inherently have higher native leakages than more mature processes, so managing leakage currents is of utmost importance," Bock says. "However, newer processes typically operate at lower voltages, thus their run currents tend to be easier to manage for the same number of transistors." But adding further features will make it more difficult to manage run currents.

Chip design innovations include greater flexibility and options to turn sections of the chip (or the whole chip) on/off more quickly along with flexible clocking options mentioned earlier. Using these techniques plus lower-power memories, such as DDR-SDRAM (double data rate-synchronous dynamic random access memory), can yield major overall system power reduction, according to Bock. Tool innovations currently center on producing training and application notes on designing for low-power systems. He also mentions Freescale simulator tools coming in the near future, which can estimate chip power usage and display it to users.

Systems view

While this article focuses on the chip/processor level, power management has a wider role. Intel takes such a holistic approach, mentioning that multi-core architectures also enable power savings at the system/rack level. "By combining multiple execution cores with commercially available virtual machine monitor software, developers can support multiple operating systems on one platform," says Ames. One core can handle a real-time operating system (RTOS) with another core running a non-RTOS. The approach also allows consolidation of dedicated servers (each supporting a separate software environment), saving power and rack space, he explains. Intel offers multi-core processors that include technology to support virtualized environments.

Power management must account for efficiencies in various system elements: voltage regulator modules (VRMs), memory devices, and the processor. "One can have a great MIPS/watt processor solution that's hobbled by a poor VRM design or overly power-hungry memory solutions," concludes Ames.

Freescale's Bock points to a typical problem for a low-power, low duty-cycle application: minimizing a processor's waking time. Since a fixed amount of work must be completed during each wake cycle, a more efficient, powerful processor can ultimately save system power, he explains, if it can do the work required in, say, 25% of the time compared to a lower-end processor. "This can be true even if power dissipation in run state is moderately higher," he says.

"Leakage current tends to be the dominant factor for the most aggressive low-power applications, where battery life needs to extend to many years," continues Bock. The typical concern here is to balance power consumed in run state (efficiency) with power consumed in sleep state (leakage/stop current). Also, availability of compilers and software tools helps designers minimize power in run mode and maximize flexibility of the power management modes, which often is key to minimum overall system power consumption, he adds.

Texas Instruments Inc. likewise takes a holistic stand. TI manages power with SmartReflex technologies, which it describes as "a combination of intelligent and adaptive silicon, circuit design, and software designed to solve power and performance management challenges at smaller process nodes."

Technologies encompassed by SmartReflex include memory and logic retention cells that support dynamic power switching, reportedly without state loss (for reducing leakage and operating voltage); sensors that adapt voltage dynamically as silicon processes and temperatures change; leakage management , which cuts power drain by switching to low-power modes in response to which processes are active; workload monitoring and prediction ; and bridge power management for DSPs and other cores.

While SmartReflex cuts static leakage power at the silicon level, it also works at system level, coordinating power consumption and performance of multiple processing cores, hardware accelerators, functional blocks, and peripherals, says TI. Part of TI's offering is a library of power management cells that provides a way to finely partition device power domains. An open software framework is available for "intelligent coordination among lower-level hardware technologies;" it also offers compatibility with OS-based and third-party power management software. System-on-a-chip design aspects of SmartReflex include advanced features: adaptive voltage scaling , dynamic power switching , and standby leakage management .

SmartReflex technologies being integrated into Texas Instruments chip devices at the newer process nodes (90 nm and below) are showing their effect. TI reports a 40x reduction in power consumption (with enhanced performance) in its OMAP2420 multi-core application processor using SmartReflex. Other ongoing TI research in power management promises even more dramatic reduction of transistor leakage power.

Solvable problem

While demand for more onboard functions in the face of shrinking chip sizes is daunting, industry experts concur that the power management problem is solvable.

To manage power, chip designers realize that not all chip resources are needed at the same time nor are they needed all the time. In the fullest realization of this notion, it will take a combination of forward-looking design, enhanced chip architecture, and hardware and software innovations to manage power in future silicon devices. Innovative minds of designers will be at work as well.