32X bandwidth boost for PCI bus

Los Gatos, Calif.— Using a dual counter-rotating ring with automatic shortest-path-first architecture to provide a fault-adaptive routing and protocol, this chip quadruples throughput and halves latency compared to single-ring PCI bus designs. This new ring connection chip provides aggregate bandwidth of 4.

04/01/1998


Los Gatos, Calif.— Using a dual counter-rotating ring with automatic shortest-path-first architecture to provide a fault-adaptive routing and protocol, this chip quadruples throughput and halves latency compared to single-ring PCI bus designs. This new ring connection chip provides aggregate bandwidth of 4.25 GHz; scales with PCI bus speed; has transparent networking for up to 256 PCI buses per system; interfaces directly with 32-bit 33 MHz PCI on the processor/memory side; supports a boost to 50 MHz PCI for existing implementations and 66 MHz for new de-signs; and implements the equivalent of TCP/IP in hardware to provide reliable interconnections. Production quantity availability due second quarter 1998.

Sebring Systems





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