ESC 2006: Atmel’s 32-bit DSC focuses on throughput, power savings
At Embedded Systems Conference Silicon Valley, Atmel Corp. announced its AP7000 family of high-performance, 32-bit digital signal controllers (DSCs), the first based on the company's high-throughput AVR32 core—claimed to consistently outperform competing 32-bit cores in industry benchmarks for performance and code density.
Atmel's AP7000 architecture allows individual dynamic configuration of the controller's four clock domains, using dynamic frequency scaling (DFS).
At Embedded Systems Conference Silicon Valley, Atmel Corp . announced its AP7000 family of high-performance, 32-bit digital signal controllers (DSCs), the first based on the company's high-throughput AVR32 core—claimed to consistently outperform competing 32-bit cores in industry benchmarks for performance and code density. High level of functional integration is a further attribute of these DSCs and includes "virtually all the functionality required for multimedia systems… as well as network switches/routers," says Atmel. Integration includes a vectored multiplier coprocessor, 32 KB on-chip SRAM, 16 KB instruction/data caches, memory management unit, DMA for high-speed peripherals, and peripheral DMA controller for data transfer among peripherals and memories without wasted processor cycles.
AP7000 family eliminates the need for an external USB controller by integrating USB 2.0 high-speed protocol (480 Mbps) with on-chip transceivers. Also integrated are two 10/100 Mbps Ethernet Media Access Control (MAC) blocks for added connectivity.
High throughput of the AVR32 core allows executing applications at a slower clock frequency than in competing processors, according to Atmel. Operating at a lower clock rates directly yield proportionately lower power consumption.
Another power saving and performance feature is AP7000's multi-layer, high-speed bus architecture that enables multiple operations in parallel—plus two peripheral bus bridges allowing use of different clock frequencies for high- and low-speed peripherals. This contrasts with a conventional bus structure, where the fastest peripheral sets the bus clock, resulting in higher power draw. Each of the controller's four clock domains can be set at the lowest possible frequency for an active function, using dynamic frequency scaling algorithms. For example, when the application is inactive, clocks for three domains (CPU internal clock, bus matrix, and high-speed bridge) may shut down, while the slow-speed bridge's clock runs to handle ongoing data transfer. "DFS cuts power by 50%," says Atmel.
First device of the AP7000 family, AT32AP7000, is available now in a 256-ball CABGA package, priced at $16.60 in quantities of 10,000. For a complete development environment, STK1000 starter kit is available at $450; Atmel's JTAGICE mk-II also is available at $299 to provide in-circuit emulation support.
For more on ESC 2006, also see Control Engineering April 6, 2006, Daily News .
—Frank J. Bartos, executive editor, Control Engineering
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