Isolating high-speed data interfaces
Technology Update: Choosing the right isolator requires knowing system requirements and which high-speed interface meets the requirements for isolating their signal paths using digital isolators.
High-speed interfaces are used for fast data transfers in data communications hubs, wireless base stations, flat-panel displays, servers, and peripherals like printers and digital copy machines. Typical distances reach from a few inches (between ICs or from board to board) up to several meters (between systems). Due to the short data link distance, ground potential differences between driver and receiver are assumed to be small, and the required common-mode input voltage range of a receiver is commonly limited to a few volts.
Increasingly high-speed interfaces are installed in industrial applications. This harsher environment presents external noise sources, such as motors and generators, which couple noise currents into the local grounds. These currents can raise the ground potential differences between bus nodes beyond the common-mode voltage range of bus receivers, causing data errors and even device damage. Implementing galvanic isolators into the signal and supply lines of the interface components removes the ground potential difference between bus nodes and limits the common-mode voltage to the driver’s output offset and assures robust data traffic.
Choosing the right isolator requires knowing the system requirements. To ease the design task, understand the most popular high-speed interfaces, low-voltage differential signaling and multi-point low-voltage differential signaling (LVDS and M-LVDS), and the requirements for isolating their signal paths using digital isolators.
LVDS is a low-voltage, differential signaling scheme used for high-speed data transmission in point-to-point and multi-drop data links. Defined in the TIA/EIA-644 standard, it is the most commonly used differential interface.
LVDS uses current drive technology, where the H-bridge output stage of an LVDS driver switches a constant current source of 4 mA alternately between its two differential output terminals (Figure 1). A single 100 Ohm resistor placed at the receiver input terminates the differential pair to eliminate reflections and also converts the line current into a differential receiver input voltage of 400 mV nominal. The differential voltage swings around a 1.2 V common-mode potential, which is the typical driver output offset voltage (Figure 2).
Typical LVDS applications include high-speed backplane communication, data transmission, and clock distribution across cables and between systems, so from board-to-board, as well as intra-circuit communication links within one printed circuit board (PCB). The two bus topologies supported by LVDS are point-to-point and multi-drop.
A point-to-point data link (Figure 3) connects a single driver to a single receiver via a pair of wires or traces. The receiving end of the link has a termination resistor. Often multiple point-to-point links are designed in parallel to increase the total bandwidth between two communication points.
In a multi-drop topology a single driver drives multiple receivers as shown in Figure 4. Because LVDS is designed for point-to-point applications, its finite drive capability limits the number of receivers that can be connected and the signaling distance that can be accomplished.
To extend LVDS technology to multi-point applications, a new standard (TIA/EIA-899) for multi-point LVDS or M-LVDS was created. M-LVDS allows higher speed communication links than RS485 or controller area network (CAN) with less power.
To support the higher bus load of multi-point applications, M-LVDS drivers have higher current drive capability than LVDS drivers. They can drive up to 32 nodes over longer signaling distances with slew-rate controlled transitions to minimize electromagnetic interference (EMI) in long cable runs. M-LVDS receivers have a wider common-mode input voltage range than LVDS receivers and provide an option of fail-safe receivers for bus idle conditions.
In a multi-point topology each bus node can either send or receive. Two types of multipoint buses exist: a half-duplex and a full-duplex version shown in Figures 5 and 6.
A half-duplex bus uses two wires across which one node may transmit while another node receives data. In a full-duplex bus, two signal pairs (four wires) are used. One pair connects the driver of a master node to the receivers of multiple slave nodes. The other pair connects the drivers of the slave nodes to the receiver of the master node. This topology allows the master to either broadcast data to all slaves or address a specific slave node, while simultaneously receiving data from the slave nodes, one slave at a time.
An important condition of a multi-point bus is bus idling, that is, when no driver is driving the bus and the differential bus voltage is zero. The output of a standard or Type-1 M-LVDS receiver, with symmetrical input thresholds of ± 50 mV, will be undefined. To assure a defined low receiver output state during bus idling, a Type-2 M-LVDS receiver has offset input thresholds of +50 mV to +150 mV.
For comparison, Table 1 lists the main driver and receiver characteristics of LVDS and M-LVDS components.
Table 1. Driver and receiver characteristics of LVDS and M-LVDS
Isolating the data link
Table 1 shows that the input voltage range of LVDS and M-LVDS receivers is limited to just a few volts, thus allowing for ground potential differences (GPDs) in non-isolated data links of not more than ± 1 V. In real-world applications, however, even short bus lengths can have GPDs of up to 30 V and more, thus exceeding the receiver maximum input voltage range by far.
Figure 7 shows a non-isolated data link. Because the receiver inputs are internally biased with reference to the receiver ground, the maximum receiver input voltage is the sum of the signal voltage (VD), the driver output offset voltage (VOS), and the voltage difference between driver and receiver grounds (GPD). Hence, whether a data link works flawlessly or suffers damage from overvoltage potentials greatly depends on GPD.
Isolating the bus components from the local node circuits (Figure 8) removes the large GPD between driver and receiver. The driver and receiver grounds are now floating. With the only common-mode component being VOS, the receiver ground assumes VOS potential. The resulting voltage difference between driver and receiver grounds is also VOS.
Thus, galvanic isolation assures robust data traffic by making the data link independent from large ground potential differences.
Careful selection of digital isolators is advised as these isolators introduce additional propagation delays, jitter, and skew, which all affect the signal timing on the bus lines. If these parameters exceed certain values, synchronicity between signals of a single signal pair and between the parallel signal pairs of a multi-channel link might not be provided.
The most important timing parameters to look for in an isolator data sheet are:
- tPLH, tPHL, the propagation delays for low-to-high and high-to-low transitions
- PWD, the pulse-width distortion or the magnitude of the difference between propagation delays, |tPHL – tPLH|
- tSK(o), the channel-to-channel skew, the difference between transitions of multiple channels
- tSK(PP), the part-to-part skew, the difference between transitions of multiple devices.
For easy comparison Table 2 (below) lists these timing parameters for a capacitive and an inductive 150 Mbps, 4-channel, digital isolator.
Table 2. Comparing worst-case timing parameters of capacitive and inductive 4-channel isolators
The parametric values of both isolator technologies are almost identical except for the large part-to-part skew of the inductive isolator. This means that as long as the potential data link is limited to 4-channels, only requiring a single isolator IC, synchronicity is warranted due to low channel-to-channel skew. For higher channel counts requiring more than one isolator device, the 16 ns skew of the inductive isolator must be compensated for using field-programmable gate arrays (FPGAs) with dynamic phase adjustment (DPA).
If, however, DPA is not available, the only way to assure synchronous data transfer is by adhering to a strict timing budget, which is easily accomplished using a capacitive isolator.
Bearing in mind that the inductive isolation technology is in its third generation, there is doubt that part-to-part skew is going to improve for inductive isolators.
Another important decision factor when selecting isolator technology is the power or current consumption at high data rates. After all, LVDS was created on the premise of providing gigabits at milliwatts. Hence, a high-speed isolator must provide sufficiently low-current consumption to honor this premise. A comparison of supply current per channel in Figure 9 shows that inductive isolators possess low-power consumption only at low data rates of up to 10 Mbps, where they typically replace optoisolators. At around 15 Mbps, however, capacitive isolators already begin consuming less current. And at data rates of 50 Mbps to 150 Mbps, the capacitive technology shows its superiority by consuming only half to one-third the current that inductive isolators require.
Budget, low power
Due to a tight time budget and low power consumption, digital capacitive isolators are well suited for isolated high-speed interfaces such as LVDS and M-LVDS. Texas Instruments provides a huge portfolio of LVDS single and multi-channel drivers and receivers, M-LVDS transceivers, and high-speed, digital isolators.
- Thomas Kugelstadt is a senior systems engineer with Texas Instruments. Edited by Mark T. Hoske, content manager, CFE Media, Control Engineering, mhoske(at)cfemedia.com.
Scroll down to see references, more about the author, and links to related articles.
About the author: Thomas Kugelstadt is a senior systems engineer with Texas Instruments. He is responsible for defining new, high-performance analog products and developing complete system solutions for industrial interfaces with robust transient protection. He is a graduate engineer from the Frankfurt University of Applied Science.
- High-speed quad digital isolators (ISO7240M) data sheet (SLLS868O), Texas Instruments, November 2012: www.ti.com/lit/slls868O
- LVDS Owner's Manual Design Guide, SNLA187, 4th Edition, Texas Instruments, November 2008: www.ti.com/lit/snla187
- An overview of LVDS technology (SNLA165), John Goldie, Texas Instruments (formerly National Semiconductor), July 1998: www.ti.com/lit/snla187
- For more information about interface solutions from TI, visit: www.ti.com/interface-ca.
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