World's first: Raytheon develops polymorphic computer

El Segundo, CA—Raytheon Co. has developed the world's first computer whose architecture can adopt different forms depending on the application.


El Segundo, CARaytheon Co. has developed the world's first computer whose architecture can adopt different forms depending on the application. Dubbed Monarch (for Morphable Networked Micro-Architecture) and developed to address the large data volume of sensor systems as well as their signal and data processing throughput requirements, it is the most adaptable processor ever built for the U.S. Department of Defense (DoD), reducing the number of processor types required.
Monarch performs as a single system on a chip, resulting in a significant reduction of the number of processors required for computing systems, and it performs in an array of chips for teraflop throughput. "Typically, a chip is optimally designed either for front-end signal processing or back-end control and data processing," explains Nick Uros, vice president for the Advanced Concepts and Technology group of Raytheon Space and Airborne Systems. "The Monarch micro-architecture is unique in its ability to reconfigure itself to optimize processing on the fly. Monarch provides exceptional compute capacity and highly flexible data bandwidth capability with beyond state-of-the-art power efficiency, and it's fully programmable."
In addition to the ability to adapt its architecture for a particular objective, the Monarch computer is also believed to be the most power- efficient processor available. "In laboratory testing Monarch outperformed the Intel quad-core Xeon chip by a factor of 10," said Michael Vahey, the principal investigator for the company's Monarch technology.
The chip’s polymorphic capability and super efficiency enable the development of DoD systems that need very small size, low power, and in some cases radiation tolerance for such purposes as global positioning systems, airborne and space radar and video processing systems. The company has begun tests on prototypes of the polymorphic Monarch processors to verify they'll function as designed and to establish their maximum throughput and power efficiency. It contains six microprocessors with a highly interconnected reconfigurable computing array and provides 64 gigaflops (floating point operations per second) with more than 60 gigabytes per second of memory bandwidth and more than 43 gigabytes per second of off-chip data bandwidth.
The processor was developed under a Defense Advanced Research Project Agency (DARPA) polymorphous computing architecture contract from the U.S. Air Force Research Laboratory. Raytheon Space and Airborne Systems led an industry team with the Information Sciences Institute of the University of Southern California to create the integrated large-scale system on a chip with a suite of software development tools for programs of high value to the Department of Defense and commercial applications. Besides USC major subcontractors included Georgia Institute of Technology, Mercury Computer Systems and IBM's Global Engineering Solutions division.
Edited by C.G. Masi , senior editor, Control Engineering
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