‘First’ EDA products aid multi-voltage IC/SoC designs

By Control Engineering Staff February 9, 2006
ArchPro Design Automation’s MVRC tool analyzes all design states to enable multi-voltage equivalence checking. Said to be an industry first, MVRC can prove that RTL and Netlist are equivalent—via third-party equivalence checkers.

Chip power management methods can contain bugs that often come to light after silicon is produced. This results in time- and cost-consuming revisions to silicon, system functions, and software. Two new electronic design automation (EDA) products from ArchPro Design Automation Inc . aid multi-voltage design processes by allowing developers, reportedly for the first time, to verify and implement voltage states with the push of a button. The company is a developer of EDA systems for low-power, multi-voltage integrated circuit (IC) and system-on-a-chip (SoC) design.
The new products are MVRC, a voltage rule checker that helps catch errors in power-managed designs, right at the register-transfer logic (RTL) level, and MVSYN, which can modify RTL to support as many voltage states as needed. “MVRC and MVSYN enable verification and implementation , respectively, of voltage states. Both tools can be used at the RTL or gate level and work with all major industry standard flows to give users a cost-effective method to reduce design cycles, design costs, and speed time to market,” according to ArchPro.
MVRC and MVSYN can be applied separately or together. When combined with ArchPro’s MVSIM product (announced in August 2005) they reportedly form the first available complete EDA solution for power management design cycles. They manage power designs, correct errors, and verify low-power designs, among other functions.
ArchPro explains that approaches from a number of other vendors require designers to hand-code level shifters, isolation gates, etc., at the Netlist stage, which is too late for understanding the impact on timing/area considerations. “MVSYN solves this time-consuming, painstaking problem. [It] can eliminate months of RTL hand-coding work for customers and can insert thousands of devices as needed, at the push of a button,” notes the company.
“Given that power management has become a key viability aspect of ICs, we find that customers are struggling with traditional flows, performing many tasks manually,” says Pratap Reddy, chairman and CEO of ArchPro. “Our solution significantly improves time to market….by automating these tasks and eliminating errors right at the RTL level. Most errors emanate from voltage states and transitions between them. Even before users write a single vector, they have feedback on the power management architecture.”

—Frank J. Bartos, executive editor, Control Engineering,