Processor IP roadmap for Embedded System on Chip applications
Cortus S.A. announced its plan to launch three new microcontroller IP cores as part of its processor roadmap. The new cores share common technology with the APS3 core, but address complementary market segments.
With the use of sensor, control systems and connectivity technology becoming ubiquitous it is essential that integrated circuits for embedded applications combine adequate processing power, low energy usage and minimal silicon area.
Under the microcontroller core roadmap, the APS3 will be complemented by two new integer and one floating point processor cores. The APS5 will support more complex processor sub-systems requiring caches, co-processors and multi-core architectures. The FPS6 single precision floating point microcontroller core will combine high floating point throughput with a small silicon footprint and low power dissipation.
For small microcontroller subsystems the Cortus will provide an entry-level 32-bit solution with the APS1 processor. This core, with a comparable silicon footprint to existing 8-bit cores such as 8051, will deliver greater computational performance and while dissipating much less power than 8-bit cores. APS1, like other Cortus processors, has been designed to be programmed with C or C++ without the need to use assembly code.
All Cortus cores share a common technology base with a modern RISC architecture and native 32-bit performance. They all can use the fast, low latency APS bus with Cortus peripherals. Cortus supplies a GNU-based APS toolchain and an Eclipse-based IDE which supports the entire product family. Ports of FreeRTOS, OpenRTOS and Micrium uC/OSII are available for the processor product range.
– Edited by Chris Vavra, Control Engineering, www.controleng.com