ChipX introduces CX6000 structured ASICs with embedded IP

Santa Clara, CA—ChipX is introducing its new CX6000 family of 12 structured ASICs, which it says offer the first, complete USB subsystem for simplifying integration.


Santa Clara, CA— ChipX is introducing its new CX6000 family of 12 structured ASICs, which it says offer the first, complete USB subsystem for simplifying integration. Fabricated in an eight-metal, 0.13-micron process, these additions to the firm’s structured ASICs reportedly accelerate time to market and reduce risk by integrating silicon-proven IP subsystems into the structured ASIC fabric.

The company says the first 12 CX6200 devices integrate an industry-standard PHY for USB 2.0 hi-speed on-the-go (OTG) applications. ChipX will supply a single-cycle per clock instruction 80515 processor, which is capable of up to 200 MHz, and a USB controller, which is proven to work with the PHY to users through IP partnerships. The combination of PHY and controller has achieved USB-IF compliance in silicon. CX6200 reportedly is ideal for PC peripheral, imaging, consumer, security and a variety of industrial applications.

'Normally, designers seeking to build USB capability into an ASIC must purchase a PHY, a controller, and a processor, integrate them into their design, develop the software, then run the entire solution through compliance testing,' explains Elie Massabki, marketing VP with ChipX. 'This process is arduous, time-consuming, and full of risk, since the various IP blocks may not communicate well. By providing our customers with a complete, compliance-capable solution, we can reduce their chip integration effort, shorten their development cycle and maximize their chance of design success.'

In addition, CX6200 also enable profitable access to highly segmented markets using the ChipX SideChip approach, which is structured ASIC that resides next to a main ASIC and provides integration relief and flexibility to a system architecture. In an increasing number of systems, in which standards are changing and markets are segmented, designers regularly need to expand the capabilities of the system. However, many can’t afford to re-spin the main system chip or build a new chip for each individual market. By mounting additional capabilities on a SideChip with an embedded USB interface, designers reportedly can meet changing market requirements, and extend the life of an existing system with minimal effort.

Overall, the company’s CX6000 family uses its silicon-proven X-Cell architecture. The firm says this architecture’s highly granular and efficient architecture delivers higher gate densities and much lower device costs when compared to programmable devices in smaller geometries. The new ChipX product family can be customized in two, three, or four layers of metal depending on users’ priority in terms of density and time to market. CX6000 also is equipped with configurable I/Os, capable of a wide range of capabilities including LVTTL, LVCMOS, SSTL18/2/3, HSTL, LVDS, LVPECL, XOSC, PCI, PCIX and double data-rate. The I/Os can be programmed with a number of parameters and can be individually configured as input, output, bi-directional, power or ground.

Meanwhile, the CX6200 product line offers 140k to 1.8M ASIC gates, up to 1.2 Mbits of embedded high-density SRAM and a maximum operating frequency of 250 MHz. It also adds four configurable, low-jitter PLLs with output frequency from 10 MHz to 1 GHz.

Control Engineering Daily News Desk
Jim Montague, news editor

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