New chip-making technology to boost processor performance
In papers presented at the International Electron Devices Meeting (IEDM) last week, the two companies announced they have successfully combined embedded silicon germanium (e-SiGe) with dual stress liner (DSL) and stress memorization technology (SMT) on silicon-on-insulator (SOI) wafers to achieve a 40% increase in transistor performance compared to similar chips produced without stress technology, while controlling power consumption and heat dissipation. The new process technologies reduce interconnect delay through the use of lower dielectric constant insulators, which can improve overall product performance and lower power consumption. The technologies can be manufactured at the 65-nm generation and are scalable for use in future generations.
Said Gary Patton, vice president, technology development at IBM’s Semiconductor Research Development Center, the joint development partnership “is key to overcoming power and heat challenges as the industry reaches near-atomic scales.”
Third-generation strain technology was developed as part of the AMD and IBM joint-development alliance at AMD’s fabrication facilities in Dresden, Germany and the IBM Semiconductor Research and Development Center in East Fishkill, NY.
—Control Engineering Daily News Desk
Jeanine Katzel, senior editor, firstname.lastname@example.org