ASICs Versus FPGAs
As with other technologies, reports of the demise of ASICs have been premature. Design starts may be down sharply, but ASIC revenues continue to impress, especially in Asia/Pacific regions. Also, alternative hybrid approaches, such as "structured ASICs" may add new life to the technology. Meanwhile, FPGAs (and other programmable logic devices) are flexing their muscles, gaining critical mass, a...
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As with other technologies, reports of the demise of ASICs have been premature. Design starts may be down sharply, but ASIC revenues continue to impress, especially in Asia/Pacific regions. Also, alternative hybrid approaches, such as 'structured ASICs' may add new life to the technology. Meanwhile, FPGAs (and other programmable logic devices) are flexing their muscles, gaining critical mass, and moving up from low-end applications.
Each technology has its supporters. Traditionally, ASICs are used for large projects and FPGAs for smaller runs that need to get to market faster, or can benefit from remote upgrades. ASIC and FPGA providers remain at odds about which may be superior and in what applications. Likely, these technologies and their variants will continue to coexist well into the future (see 'silicon approaches' sidebar).
Major drawing card for FPGAs remains 'time-to-market value,' says David Greenfield, senior director of high-density FPGAs at Altera Corp. 'It's driving FPGA adoption over ASICs for the vast majority of design starts today,' he says. 'While ASIC technology clearly has a value proposition where performance, density, and unit volume requirements are very high, FPGA's advances and ASIC's increasing development costs are pushing ASICs into an ever-shrinking niche.' Improved FPGA performance, density, and fabrication cost are behind this trend.
In the past, high-performance/functionality clearly differentiated ASICs from FPGAs, which 'had neither,' according to Greenfield. Much of that has changed with chip fabrication moving from 180 nm (0.18 micron) to 130 and 90 nm processes, which now enable FPGA performance to satisfy 'all but the most demanding applications' and the density range of nearly 80% of logic designs, he explains. 'Some system architects are also realizing that ASIC's niche of extremely high-performance/density holds excessive risk. NRE [non-recurring engineering] and development costs are highest for [such] products.'
Earlier FPGAs were only viable for prototyping or low-volume/density applications; now they see very high-volume usage in consumer products and other moderate volume high-density applications, says Altera. (See typical volume figures in an Online Extra article.) Highest-density FPGAs (90 nm) still have a definitive higher unit price than ASICs, explains Greenfield. 'However, cost trade-offs often favor FPGAs even with these highest density applications, when development and NRE charges are factored in,' he states.
At Texas Instruments (TI), focus on ASICs centers on a cell-based approach, serving a limited number of large customers in need of very complex, high volume devices with average gate count typically five times that of standard industry ASICs. Applications requiring a high degree of 'competitive differentiation' in networking and telecom comprise the markets.
'Upfront development investment is higher with a cell-based ASIC approach,' concedes, John DiFilippo, silicon architect for TI's ASIC Communications Infrastructure Business Unit, 'but at high volumes, ROI is significantly better due to smaller die size and lower per unit costs. FPGAs tend to be a better choice where unit price is less important, or time-to-market, or low initial development cost drives the solution.'
DiFilippo considers TI's customer requirements for 'cost and performance mix' to be beyond those achievable with an FPGA or structured ASIC, which he thinks better fits broader, mid-range markets. 'FPGAs and structured ASICs are suitable for low volume, short lifetime applications where customers can compromise on functionality and performance while still achieving their system objectives,' he says.
Yet, the company recognizes competing technologies. It has built newer enabling features into its cell-based ASICs to deliver gate-array-like flexibility, shorter cycle time, and more cost-efficiency if the design requires a re-spin. TI also has developed 'platform' ASIC products that can be leveraged across multiple customer lines, which it says offer lower per-system development costs.
In TI's view, a cell-based ASIC approach best fits one or more of these scenarios:
Gate and memory-bit counts of more than 10 million, each;
High number of giga-bit links;
Master clock speeds greater than 300 MHz at lowest achievable power; and
Highly cost-sensitive applications.
Xilinx Inc. cites a near-decade-long debate over FPGAs as a 'viable alternative' to ASICs and related standard devices. Despite FPGAs' remarkable progress over that time, designers until recently had to use the largest, more costly devices to obtain high-performance features—DSP, RISC processing, or high-speed serial connectivity—needed for a specific application, states Erich Goetting, vice president and GM, Xilinx Advanced Products Div.
Now, Xilinx offers new 'domain-optimized platform FPGAs' (Virtex-4) that promise application scaling for required features and cost goals based on the company's ASMBL (modular block) architecture. 'ASMBL is a modular framework of silicon subsystems, enabling a new FPGA development method for rapid, cost-effective deployment of platforms targeted to different application domains,' says Goetting. For example, a given design may need high DSP functionality but not necessarily high-level logic. With ASMBL architecture, Virtex-4 lets users pick the right mix of logic, DSP, memory, and other functions (grouped in columns) for a specific design. The columnar architecture is also said to allow a selection of up to 17 devices and up to an order of magnitude more capability 'for a given price point.'
Xilinx points to an overall cost benefit for FPGAs due to essentially zero NRE charges (typically absorbed by FPGA vendors). 'Rapid, significant increase in ASIC development costs clearly tips the advantage to using increasingly capable platform FPGAs,' continues Goetting. 'Apart from their breadth in the analog/mixed-signal space, ASICs can't offer significant functionality advantages over FPGAs.' Other cost savings with FPGAs include implementing bug fixes and tuning system performance for new requirements via software download.
GE Fanuc Automation sees FPGA's 'true benefits' in two areas: ability to quickly start a development using a reliable standard part that's easily modified to add features, and ability to fix bugs found during development or over a product's life. FPGAs, unlike ASICs, come with extra functions built in as standard—for example, testability or a JTAG interface—saving design time and cost, cites Richard Reed, GE Fanuc senior staff engineer.
FPGAs speed up product introduction. 'High volume use of standard parts also makes them quite cost competitive with ASICs,' says Reed. 'Longer lifecycles of industrial products and application volume will dictate whether it becomes cost-effective to transfer the design into a hardcopy or ASIC version of the design,' he adds.
As for ASICs' benefits, Reed mentions they're ready to run immediately on power up, have more package options per size of logic, and may include some analog logic. In contrast, FPGAs need time to load their configuration into memory, so they're not immediately functional. Also, they come in fixed packages.
Nallatech Inc., a developer of systems and hardware/ software for FPGA computing, concedes that ASICs offer 'high performance levels' for the type of functionality and specific application to which they're dedicated by design. However, using ASIC technology to implement high-performance processing functions, such as industrial simulation, modeling, or imaging carries 'commercial implications,' notes, Craig Sanderson, Nallatech systems applications engineer.
Often, these 'performance' applications have low/medium volume. Without trying to define a crossover point where ASICs would become cost-effective, Sanderson says, 'ASIC implementations for relatively low volume applications are not commercially viable from a cost/risk perspective.' Regardless of volume, 'FPGA vendors will generally advocate using FPGAs instead of ASICs,' he adds.
Nallatech concurs that FPGAs avoid high NRE costs and cites other advantages. Reprogrammability of FPGAs allows a more flexible development path, reducing risk and cost. It's unlike an ASIC application development that must be 'right first time.' Field reprogrammability adds ability to modify the chip in a running application—not replace it—using service packs or application upgrades. An FPGA can even be upgraded remotely over the Internet. Obsolescence control refers to existing FPGA application designs acting as a source to be recompiled for future generation devices.
FPGA providers increasingly claim performance 'comparable' to ASICs for many applications. Sanderson states, 'For high-performance applications, FPGAs offer sufficient logic resources to enable implantation of functionality that performs at a level equivalent to that of ASIC technologies and at considerably higher performance levels than standard processors.'
Since FPGAs are reprogrammable, applications can be tested in real hardware. 'With ASICs, all testing has to be done as simulation before the design is developed into the physical ASIC hardware—by which time finding any bugs is too late,' adds Sanderson.
Gricha Raether, industrial control and distributed I/O product manager at National Instruments (NI), notes early use of ASICs and FPGAs in large volume applications, such as machine building and OEM-type integration, which could amortize the historically high development costs. He attributes high costs to long development cycles and need for extensive expertise with development tools for these devices. ASICs in particular are prone to time-intensive design and fabrication steps.
FPGAs are supplied more complete, ready for programming. In that sense, FPGAs eliminate the need for production of the actual integrated circuit (IC), he explains. However, because of FPGA's flexibility to be customized, suppliers could charge a premium. For either technology, but more for ASICs, additional cost goes to designing the enclosure and printed circuit board that support the IC.
Raether believes that FPGAs offer benefits even for longer lifecycles of industrial products. This stems from ability to be easily reprogrammed for new revisions or be reprogrammed in the field. 'Designers using FPGAs need to account for possible extensions or modifications that might be necessary, and adopt them when choosing FPGA size in terms of available gates,' he says. It entails a delicate balance between cost as a function of number of gates and added features to be programmed onto the chip—plus the 'space' needed.
Altera agrees that FPGAs offer 'tremendous value' even for longer industrial product cycles that can include declining sales over time. 'Lack of minimum order quantities and longer life of FPGA processes is a tremendous differentiator,' says Greenfield. 'Many industrial customers who designed ASIC product five years back are now replacing ASICs with FPGAs.' Reasons include inflexible ASIC minimum order quantities, now obsolete ASIC process nodes, or need to convert to a lead-free chip package.
Process obsolescence is a fact of life for chip manufacturers. 'This issue is much more severe for ASIC companies because they tend to have a much more limited customer base and are more likely to have a captive fab,' adds Greenfield.
Role of software tools
Developing FPGA solutions is complex, requiring appropriate software tools. Nallatech's Sanderson mentions that FPGA design tools are improving, particularly tools that apply high-level languages or interfaces to develop applications, such as MatLab/Simulink from the Mathworks. (More design tools are listed in an Online Extra to this article.)
He explains that high-level languages are especially important in FPGA computing because they permit wrapping the necessary application functions into one or multi-device FPGAs. Previously, these 'functions would normally have been carried out on one or more DSPs or microprocessors combined with some fixed-function ASICs,' says Sanderson.
One example of design complexity facing developers is establishing communication among various multiple functional blocks in a single FPGA. The company's DimeTalk tool (currently available only for Nallatech hardware) reportedly overcomes challenges specific to developing system communications within FPGAs.
Each chip technology requires design tools. FPGA users are shielded from concerns of manufacturing yield and submicron issues by the nature of FPGA design flow that also brings ease of use, cost, and time-to-market benefits, says Xilinx. 'As standard products, FPGAs arrive fully tested and physically functional—the FPGA supplier handles physical design, verification, and characterization,' adds Goetting. Xilinx offers integrated design and debug tools for logic, DSP, and embedded processing, plus interfaces to third-party tools.
Depending on the provider, software to program FPGAs varies in content and value-add features like compilation and editing tools. NI's Raether stresses that using these tools proficiently requires years of experience and education. 'Some higher level tools are slowly making their way into the market. However, they still require a good understanding of FPGAs' internal mechanics,' he says. VHDL (very [high speed] hardware description language) is the most common development language used. Raether claims NI's LabView is the only currently available software that completely abstracts a device's internal workings. It allows programming of FPGAs contained in programmable automation controllers (PACs) via the graphical development environment.
Challenges, hybrid solutions
FPGAs have their own challenges. Xilinx mentions static power consumption and die size constraints at higher densities, because programmable chips need more transistors to implement the same logical function. Process-, circuit-, and architecture-level innovations are seemingly meeting power limitations even as FPGAs move to new, smaller-geometry process nodes. For example, Xilinx reduced power consumption by 50% in its 90-nm Virtex-4 family versus its 130-nm predecessor by using triple-oxide technology and integrated platform functions, says Goetting.
National Instrument's Raether notes challenges of time, compliance with industrial specs, and allotting appropriate development resources in designing circuit boards and enclosures to house the FPGA. Devices such as NI CompactRIO (photo) include an FPGA to help streamline such product development tasks.
GE Fanuc's Reed is keen on application-specific standard product (ASSP) parts, which derive from varying traditional ASIC design. IP (intellectual property) cores are available, which GE Fanuc uses in FPGAs to aid its productivity; vendors use the same techniques to create many modifications of a standard part to hit smaller niche markets, he says. 'We are able to get an embedded processor with a better mix of what we need—and without paying for what we don't need—due to reusable cores that can be put together fairly quickly to make a standard part,' concludes Reed.
'Application-specific' or 'field-programmable,' that is the present question. Whether it's 'nobler in the mind' to go with hybrid chip solutions will play out in the near future.
ASIC, FPGA pros and cons
A common theme from contributors to this article is the importance of reprogrammability to programmable logic devices. Xilinx Inc., for one, stresses FPGA’s ability to be reprogrammed repeatedly—even after deployment in the field.
Xilinx also sees longer design and verification cycles for ASICs, with its high likelihood of a design “re-spin”and associated penalties. Additional, costly verification tools, training, and resources are also required, explains Erich Goetting, vice president and GM, Xilinx Advanced Products Div. The company supplies tools for its FPGA products, including boards, support, and reference designs. “Xilinx tools are available online as free evaluation versions,” adds Goetting.
GE Fanuc Automation’s senior staff engineer Richard Reed also mentions the part obsolescence associated with ASICs that can call for costly, time-consuming redesign during the lifetime of a product. In his experience, redesign has not been needed for FPGAs.
FPGA provider Altera Corp. mentions only niche and custom applications for ASICs. An example cited was an application where integrating analog or special functions on an ASIC fabric was an important requirement.
FPGA volumes, costs
David Greenfield, Altera Corp .’s senior director of high-density FPGAs, put some perspective on volume figures associated with FPGAs. For example, at the prior 0.18 micron process, typical volume applications were in the range of tens of thousands of units, with 100k units being unusual—while at 0.13 micron, typical purchases are 100k units and the “unusual” point has moved to one million units. At the highest density processes, some buying goes on at tens of thousands of units. “Early results at the 90-nm process show an acceleration of the volume trend,” he says.
Attention to overall development costs applies to FPGAs as well. Especially the relatively high cost of configuration devices needs management, which in the past has accounted for as much as 30% of total cost of FPGAs supported, according to Altera. The company has recently sought to drive configuration costs down to around 10% of total cost, via new serial configuration devices used during FPGA power up and other times of system operation.
The hybrid technology of “structured ASICs” resides in the middle ground between application-specific and programmable-silicon devices, and seeks to provide the best of both worlds. (See main article sidebar for definition of the different technologies.)
By incorporating prefabricated elements common to many designs (and the needs of more customers), structured ASIC devices reduce heavy, up-front non-recurring engineering (NRE) costs associated with cell-based ASICs. This also helps shorten development time. Of course, selection of specific elements to be prefabricated is crucial. Structured ASICs reportedly approach the performance level of cell-based ASIC devices.
Supporters claim that structured ASICs can cut development cost by 25% compared to a standard ASIC in a complex application, and cut unit cost by about 90% versus a complex FPGA.
Structured ASICs have their own organization. Founded by the collaboration of four manufacturers and tool providers— ChipX , Lightspeed , Synplicity , and Tera Systems —the Structured ASIC Association (SAA) seeks to establish and promote this technology as a unique semiconductor market segment, as well as providing education to the industry.
Xilinx has no particular positive spin for this sector. It considers structured ASICs (and standard-cell ASICs) as “ultimately limited by the‘ASIC methodology’ “ itself and by its lack of flexibility. The company sees fewer investments going to large ASIC hardware design/verification efforts and its associated expenses.
Texas Instruments adds that gate arrays and structured arrays offer some middle ground between ASICs and FPGAs from a cost perspective. “However performance and power still substantially lag the cell-based ASIC approach that TI delivers,” says John DiFilippo, silicon architect, for TI’s ASIC Communications Infrastructure Business Unit.
Applications, more software tools
The main article illustrated examples of FPGAs implemented in industrial products: a reconfigurable I/O acquisition and control system from National Instruments (CompactRIO) and a process automation controller from GE Fanuc (PACSystems RX3i).
Another recent industrial area that’s developing for these chip devices is in vision systems. Actually, both an FPGA and an ASIC are part of Matrox Imaging’s recently announced Odyssey Xpro+, which is an enhanced version of its scalable vision-processor board. Matrox Odyssey Xpro+ is powered by a Freescale G4 Power PC embedded microprocessor with a core frequency starting at 1.4 GHz.
The ASIC element is a combination processor and router that Matrox refers to as a “pivotal component” on all boards in its Odyssey family. According to Matrox, this in-house designed high-density ASIC (with more than 30 million transistors) integrates a CPU bridge; main memory controller; a parallel processor core (or Pixel Accelerator, PA) that accelerates various mapping operations; and a router, which controls all data movement internal and external to the processing node.
The FPGA part of the device is a configurable co-processor that regulates operations not accelerated by the PA. This co-processor is based on an Altera Stratix II FPGA device, which serves to accelerate process tasks like binary operators and large look-up table mapping.
Craig Sanderson, Nallatech systems applications engineer notes the availability of other software tools and high-level languages for FPGA development. Among them are: Handel-C, System C using tools from Celoxica Ltd. ; Mitrion-C using tools from Mitrion ; and Impulse-C using tools from Impulse Accelerated Technologies .
Other technology suppliers
Here’s a less than exhaustive list of additional manufacturers and suppliers that address technologies covered in this article.
Company Technology area(s)
Similar, yet different silicon approaches
ASICs and FPGAs are all integrated circuits (ICs), but with a difference. Application-specific integrated circuit (ASIC), as the name implies, is a silicon chip hardwired to meet specific application needs of one electronic product or range of products. It's found in myriad consumer and industrial products.
Field-programmable gate array (FPGA), a more recent IC development, incorporates thousands of logic cells linked by programmable switches that logically interconnect cells to meet different design requirements. Besides logic blocks, other programmable elements of an FPGA are I/O blocks that serve as the interface between internal signal lines and the chip's external pins, and interconnects that route I/O signals of the other elements to appropriate networks. Ability to be reprogrammed is the key drawing card of these devices.
Structured ASIC forms a middle ground between the above approaches, using base metal layers to prefabricate design elements common to many applications (logic cells, memory, I/O, etc.). Specific customization is added later in the final few metal layers, with savings in much fewer mask layers and up-front costs.
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