Solutions aid embedded hardware control
Microsoft Windows CE's expansion into embedded systems and industrial controls is challenging developers trying to help applications communicate with a growing range of hardware devices. Some developers face time-critical tasks requiring enhancements—often involving long and nondeterministic latencies—to specific Windows CE areas.
Microsoft Windows CE's expansion into embedded systems and industrial controls is challenging developers trying to help applications communicate with a growing range of hardware devices. Some developers face time-critical tasks requiring enhancements-often involving long and nondeterministic latencies-to specific Windows CE areas.
Fortunately, there are several ways to solve latency problems. For example, WinDK for Windows CE from Blue Water Systems (Bellvue,Wa.) offers device driver development to solve time-critical hardware control. It builds on the kernel infrastructure, adding features and a driver development environment. Besides a WinDK for Windows 2000 interface, WinDK for Windows CE includes a class library for development and a code generation wizard that creates a starting point for development.
Other features include: Bus Master DMA for high-performance device drivers, including hardware scatter-gather support; slave DMA support; support for overlapped I/O and request queuing; interrupt handling; interrupts transparently shared across multiple devices; full enumeration of ISA, PCI, and PCMCIA buses; multiprocessor support; and performance analysis.
This shows how a typical time-critical extension (TCX) with interrupt service routine (ISR) runs with a rogue thread.
Time-Critical Extensions (TCX), an extension to Windows CE, also solves the problems of long and nondeterministic interrupt service thread (IST) latencies when developing high-performance device drivers for Windows CE. TCX adds support for true-nested kernel interrupt service routines (ISRs) plus high-speed kernel timers.
For instance, the top graph shows a situation where a rogue thread is running, and a periodic interrupt is present. In this case, average latency to the ISR is 5
A key requirement for deterministic interrupt latencies is support for ISR pre-emption. ISR pre-emption means that when an ISR is executing and a higher priority interrupt is asserted, the current ISR is preempted and processing of the higher interrupt priority begins. This condition is also called interrupt nesting. Afterward, the original interrupt processing is resumed.
TCX includes a priority scheme for nested kernel interrupts. Priorities are set up via registry entries. A mask for each of 16 interrupt levels is defined. The mask for each interrupt specifies what other interrupts, beside itself, will be masked during execution of the interrupt. Interrupt masks allow a simple interrupt priority to be established, such as making interrupt level 0 always a higher priority than any other interrupt. More complex relationships also can be defined.
Interrupt 7 preempts interrupt 6 in a nested kernel interrupt to obtain low latencies.
The lower chart shows an example where interrupt 7 is set to the highest priority and interrupt 6 has begun to execute. Interrupt 7 now fires and preemps interrupt 6. After interrupt 7 completes, interrupt 6 processing is resumed. By selecting certain interrupts to be at higher priorities, very low latencies can be consistently obtained on the important interrupts.
In addition to nested kernel ISRs, TCX adds kernel timers. These timers act in a manner similar to kernel ISRs. They can be programmed to be periodic at high frequencies. Timer frequency depends on the platform being used and the clock settings configured. Timer jitter will be similar in size to interrupt jitter.
As opportunities for Windows CE developers grow, the need also increases for tools that simplify hardware device control, such as WinDK for Windows CE. Turning projects around quickly and getting to market can make the difference between success and releasing another 'me-too' product.
William Kyle, vp, Blue Water Systems firstname.lastname@example.org
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