Synchronizing industrial Ethernet networks

06/03/2014


Distributed clocks push precision to the nanosecond level

Figure 3: This drawing shows how propagation delay between the reference clock and other DC devices is calculated. EtherCAT devices with and without DC functionality can be mixed freely with no impact to the synchronization quality of the network. CourtesAs another way to implement synchronization, EtherCAT is an example of an industrial Ethernet system that uses distributed clocks (DCs). These DCs are built into the associated EtherCAT slave controllers (ESCs), so there is no external circuitry, or special infrastructure required for implementing DCs. ESCs are the IC chips that implement the EtherCAT protocol in hardware. Devices with and without DC functionality can be mixed freely in the same network with no impact to the synchronization quality of the network. The EtherCAT specification dictates the frequency and quality of the DC device's oscillator. Therefore, there is no need for a BMC determination to be made. Any DC device can be the reference master clock. By operating principle, the reference clock is always the first EtherCAT slave that has DC functionality enabled. The advantage of this is that there is no negotiation required, and all slave devices have the same oscillator quality. Furthermore, the method of distributing the time from the reference clock is extremely efficient and elegant (see Figure 3).

Because of the processing-on-the-fly operating principle of EtherCAT, every frame is effectively routed in a cut-through fashion through every slave of an EtherCAT network (up to 65,535 slaves). Regardless of which slave is, or is not, being addressed, every frame goes through each slave device in the same path every time (there is no active routing of frames). This results in the same timing throughout the network. Each slave can predictably calculate how long it takes for data to pass between the forward direction (Tx) and returning direction (Rx), and the master also knows the exact EtherCAT network topology. This is important because the master can easily calculate the propagation delay between any two points in the network with these sets of data, such as between its reference clock (always the first DC-enabled device in the network) and each additional DC-enabled slave. This calculation needs to be done only once for a given network, and is completely topology-independent.

After calculating the propagation delay from the reference clock to an individual slave, this value is given to the slave, and each slave receives its unique propagation delay value. This is done so that each slave can set and maintain its local clock to that of the reference clock. For drift compensation, the master simply adds a very small instruction (16 bytes) to every cyclic frame, which grabs the time from the reference clock and distributes it to all other slaves. Each slave will compare the sum of the received time value from the reference clock, plus the propagation delay to its own local clock value and determine if it is running fast or slow. Compensation is done simply by adjusting how much time is counted for each pulse of its local oscillator, thereby closing a phase loop to the reference clock.

The performance of DCs is independent of the network topology, number of slave devices, and jitter of the frames coming from the master. Real-world jitter values of less than ±100 nanoseconds are regularly achieved. The main factor in tightening the phase lock loop is simply the need to issue the time distribution command more often. Because neither the jitter of the network nor the timekeeping of the individual slave devices is impacted by any jitter of the Ethernet frames, the EtherCAT network doesn't require any special master card to facilitate jitter-free frames. As long as the data are received by the farthest slave prior to the network-wide time interrupts to use it, there are no problems with frame jitter. All EtherCAT masters calculate how far in advance they need to begin sending out the frame based on any NIC jitter, any delay and jitter in the network, as well as the length of the frame itself.

Additionally, the DC unit that facilitates this synchronization doesn't require the additional complexity or cost of a microcontroller. So, even low-cost digital I/O can be constructed of only the EtherCAT slave controller chip, an EEPROM, and the driver circuitry for the input/output signals. Yet this can deliver output signals that can be commanded down to the nanosecond, or latch in time values on rising or falling signal edges (configurable) with the same nanosecond resolution, all without the addition of a microcontroller.



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