Ladder Logic 306: Simulation

Using simulation for ladder logic allows users to test advanced situations that otherwise wouldn't be possible, reducing potential costs and hazards for users.

In a basic programmable logic controller (PLC) training class, pushbuttons and pilot lights built into a trainer are used to complete exercises, usually to illustrate the use of different instructions on the PLC software platform. Advanced classes concentrate more on the techniques used in programming such as auto sequences, part tracking, and other system functions.

Making all of the elements of a properly organized program operate together can be a daunting task. All of the different types of routines relate to each other. For contacts that represent the state of a machine or sequence they are easy enough to test. Internal memory bits indicate things like auto/manual mode, autocycle, and even faults.

Inputs and outputs, however, are a different story. In a larger machine or system, they represent a lot of different types of sensors or output devices. With the trainers that are often used in training classes, there are not enough buttons, switches, and pilot lights to substitute for real-world devices. Also, input devices such as buttons, switches, and potentiometers don’t react automatically in real-time to sequences and output commands.

This is where a simulation routine can be useful. With the output logic shown in Figure 1, the inputs and outputs are "aliased" to memory bits rather than real world input/output (I/O).

If the Z-Axis_Lower_SV output is activated in a real machine (Figure 2), the Z Axis Lowered sensor usually would be activated automatically. Since this is not a real solenoid valve driving an air cylinder with a sensor on it, we need to simulate the sensor activation.

This timer circuit does the job nicely. Notice that a memory bit needs to be used to simulate the input. Input memory bits also can be used in the auto sequence to step from one sequence state to the next. The EnableOut bit is used in case a fault needs to be simulated. If the bit is disabled, it is as if the output activated but the input was never detected. The fault timer will time out and latch a fault condition.

Also notice that a "latch" or "set" bit is used for the input. This is especially important for solenoid valves that are turned off when the sequence proceeds to the next step. When the output goes off, the simulated sensor will stay active.

It is best to put all of the simulation rungs in a separate routine. If the program is designed for training and a real machine, the simulation routine can be removed or disabled later. Simulated I/O also can be replaced later with the real stuff.

With analog values, a timer is used for the simulation. In this case, the tank level will increment by five every 20 ms. Both the timer value and the tank level addend can be adjusted to achieve the desired result. There is more conditioning that should be done to simulate a real tank, but Figure 3 shows the general idea. To drain the tank, use a subtract instruction. This also can be used to test proportional-integral-derivative (PID) instructions.

Real equipment often is not available during the design phase of a project. Simulation allows programmers to test some of the more critical code before deploying it on a machine. With a human-machine interface (HMI), programmers even can visualize the process via animated objects.

Frank Lamb is the founder of Automation Consulting LLC, and is a member of the Control Engineering Editorial Advisory Board. This article originally appeared on Automation Primer’s blog. Automation Primer is a CFE Media content partner. Edited by Chris Vavra, production editor, Control Engineering, [email protected].

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Keywords: Ladder logic, simulation

Using simulation in ladder logic can allow programmers and users to test inputs and outputs before they’re implemented.

Simulation also allows programmers to test some of the more critical code before deploying it on a machine. 

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Which applications would benefit most from ladder logic simulation?